Responsibilities and Achievements

Support Technology Developmentralph lauren polo shirts Center (for 90nm development & TI’s 90nm UPP8M Transfer)ralph lauren polo shirts
Support 90nm TDSRAM Development and TI’s 90nm UPP8M product transfer, my primarily job including:-Studies on the Probe yield & Bin failure. Co-work closely with Process Integration to resolve the issues/failures;-Split Analysis/ Inline & WAT Correlation Analysis / EFA / PFA;
-Study on Test & product knowledge;ey achievements:1.Identify the soft-bitline fail due to CT punch-through the salicide, leading tohot women's dresseshot women's dresses bulk transistor turn on;2.Identify high SRAM fail due to cell N/P ratio drift;3.Identify too high IDDQ failure, improve by: (a) cool down device, (b) improve Contact uniformity, (c) fine tune STI loopSupport FAB2&FAB7 improving the yield of production product (0.16um 64M SDRAM -- License Product）from almost zero to ~98%, my primarily job including:1.Product Yield Improvement. The activities include:Studies on the Probe yield & Bin failure. Co-work closely with customers & Process Integration to resolve the issues/failures;-Perform EFA & PFA & Lay-Out check to identify issue such as low yield, low repair rate, customer return sample analysis;-Correlation analysis bin to WAT parameter & inline;2.Engineering Evaluation. The activities include:-Process Split Experiment analysis;-TTR (Test Time Reduction) evaluation to improve Testing throughput;
-Provide technical support for thecheap polo cheap polo shirtsshirts Sales;Key achievements & awards:1.Identify sort2 low repair rate issue: High LongRAS fail in sort1 and can’t repair, correlated to lower Vt and small Poly CD, and recover thousands of wafer suffer this issue through loosing the test spec & grade the the product by refresh time;2.Identify the Flip-Bitline fail;3.Identify photo reticle DC fail due to Via2 missing in sensing area by Mosaid analysis & lay-out check;4.Identify serious random DC fail due to Top metal high density defect (Too small roller of small cart for lot transfer, leading to non-smooth on FAB7 mesh-floor);5.Help analysis TTR experiment and improve testing throughput ~30%;6.SMIC 5th CIT competition the 1st prize (“V” Scheme: Recover 30~40% Yield for FAB7 Thousands of wafers);http://www.avalanchers.co.uk
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